Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever increasing variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Generally, the principle underlying the storage of data in magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit, i.e., the logic state of a “0” or a “1.”The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle, the higher its coercivity.
A prior art magnetic memory cell may be a tunneling magneto-resistance memory cell (TMR), a giant magneto-resistance memory cell (GMR), or a colossal magneto-resistance memory cell (CMR). These types of magnetic memory cells are commonly referred to as spin valve memory cells (SVM). FIGS. 1A and 1B provide a perspective view of a typical prior art magnetic memory cell having two conductors.
As shown in prior art FIGS. 1A and 1B, a magnetic spin valve memory cell 100 generally includes a data layer 101 (also called a storage layer or bit layer), a reference layer 103, and an intermediate layer 105 between the data layer 101 and the reference layer 103. The data layer 101, the reference layer 103, and the intermediate layer 105 can be made from one or more layers of material. Electrical current and magnetic fields may be provided to the SVM cell 100 by an electrically conductive row conductor 107 and an electrically conductive column conductor 109.
In a typical MRAM device, the SVM cells 100 are arranged in a cross-point array. Parallel conductive columns, also referred to as word lines, cross parallel conductive rows, also referred to as bit lines. An SVM cell 100 is placed at each intersecting cross-point between a row and column. By selecting a particular row and a particular column, a specific SVM cell 100 may be selected. A typical MRAM cross-point array may easily consist of at least 1,000 rows and 1,000 columns uniquely addressing 1,000,000 SVM cells 100.
The data layer 101 is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization M2 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M2 of the data layer 101 representing the logic state can be rotated (switched) from a first orientation, representing a logic state of “0”, to a second orientation, representing a logic state of “1”, and/or vice versa.
The reference layer 103 is usually a layer of magnetic material in which an orientation of magnetization M1 is “pinned”, as in fixed, in a predetermined direction. The direction is predetermined and established by microelectronic processing steps employed in the fabrication of the magnetic memory cell.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer 101 and the reference layer 103. For example, when an electrical potential bias is applied across the data layer 101 and the reference layer 103 in an SVM cell 100, electrons migrate between the data layer 101 and the reference layer 103 through the intermediate layer 105. The intermediate layer 105 is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling.
The logic state may be determined by measuring the resistance of the memory cell. For example, if the overall orientation of the magnetization in the data layer 101 is parallel to the pinned orientation of magnetization in the reference layer 103, the magnetic memory cell will be in a state of low resistance, R. If the overall orientation of the magnetization in the data layer 101 is anti-parallel (opposite) to the pinned orientation of magnetization in the reference layer 103, the magnetic memory cell will be in a state of high resistance, R+ΔR. The orientation of M2 and, therefore, the logic state of the SVM cell 100 may be read by sensing the resistance of the SVM cell 100.
The resistance may be sensed by applying a voltage to a selected SVM cell 100 and measuring a sense current that flows through the SVM cell 100. Ideally, the resistance is proportional to the sense current.
However, sensing the resistance state of a given SVM cell 100 in the cross-point array can be unreliable. All of the SVM cells 100 within the array are coupled together through the parallel sets of row and column conductors. The resistance of a selected SVM cell 100 at one cross-point equals the resistance of the memory cell at that cross point in parallel with the resistances of the unselected SVM cells 100. The cross-point array may be characterized and described more simply as a resistive cross-point device.
The isolation of a specific SVM cell 100 may be obtained through the use of diodes and transistors—having a non linear element in series with every linear element. With an applied bias the desired non linear element may be a low resistance while all others remain at a high resistance. However, placing diodes or transistors with each SVM cell 100 is costly in manufacturing efforts, time and physical space.
A possible alternative relies on the concept of equi-potential. Simply stated, if the same voltage is applied on both sides of a resister no current will flow through the resister. For a memory component, applying the same voltage to multiple SVM cells 100 likewise attempts to insure that no current flows through. When the resistance is changed in a selected SVM cell 100, the current flow through that particular SVM cell 100 can be detected and its state inferred.
To employ an equi-potential system in an array with a few elements is relatively easy. However, MRAM cross-point arrays having 1,000 or more rows and columns require very precise control to balance the voltage on either side of the resister (i.e. the SVM cells).
FIG. 2 provides an illustration of a prior art resistive cross-point memory array 200. Column conductors 201, 203 and 205 cross row conductors 207, 209 and 211. Resistive devices, such as SVM cells 213, 215, 217, 219, 221, 223, 225, 227 and 229 are placed at each cross-point. Each row and column also exhibits resistive properties illustrated as resistors 231, 233 and 235. Also provided are an adaptive pre-amplifier 237, capacitor 239, voltage source 241 and digital to analog converter 243.
A voltage may be applied to specifically selected SVM cell 215 by power conductor 245 running to a switching element 247, selecting column 203 and switching element 249 selecting row 209 and connecting to a ground or other low voltage. Thus is established a power path, represented as dotted line 251, running from the capacitor 239, through the selected SVM cell 215 to a ground or other low voltage. In an equi-potential setting, the most variable voltage applied to the cross-point memory array 200 is the one on the selected column line 203. As such, it is desirable that the voltage on the selected column 203 be very close to the voltage supplied to the unselected resistive devices, for example the remaining SVM cells.
To permit this control an adaptive pre-amplifier 237 may be employed. In this setting the adaptive pre-amplifier 237 is provided with a voltage VA and generates a sense voltage VA′, in theory reflecting the voltage actually delivered to the selected SVM cell 215.
However, it will be appreciated that the voltage VA′ is a local sense voltage, the sample being taken from before the voltage actually has reached the selected SVM cell 215. As conceptually illustrated, selected SVM cell 215 is at the center of the cross-point memory array 200. As such, the power path travels through a number of elements, each of which adds a resistance.
As shown, there is the resistance of the power path 251, illustrated as resistor 253, resistance at the switching element 247, and along the column 203, illustrated as resistors 233 and 235. If SVM cell 213 was the selected SVM cell, additional resistance would occur, illustrated as resistor 231. If SVM cell 217 was selected, resistance from resistor 233 would not be encountered.
As such, the local sense may have a significant amount of variance depending on how close to or how far from the selected column the selected SVM cell falls. As a result the equi-potential balance of voltage may be off, permitting an undesired transfer of current, (commonly know as sneak current or parasitic current) through unselected SVM cells.
Given the propensity for sneak current to occur in the memory array 200, the design parameters of memory array 200 are generally accommodating to these undesirable currents. Although very slight, this accommodation does impose larger components resulting in a subsequently larger memory array 200.
Hence, there is a need for an ultra-high density resistive device, such as a magnetic memory device, which overcomes one or more of the drawbacks identified above. The present invention accomplishes this objective, among others.